MicroZed Chronicles: SDSoC & MicroBlaze

Several times throughout this series we have looked at how we can use SDSoC with both the Zynq and the Zynq MPSoC for a number of different boards.

However, we can also use SDSoC if we are developing a MicroBlaze-based solution. Just like with the Zynq and Zynq MPSoC, this allows us to use SDSoC to implement accelerators in logic, without having to create them in RTL or HLS first.

To use SDSoC with a MicroBlaze solution, we first need to convert our Vivado design, which includes the MicroBlaze processor into a SDSoC platform.

In order to be compatible with SDSoC, we must ensure sure that our MicroBlaze system is self-contained and includes at least a LMB Memory, MDM, AXI Timer, and UART. Although to get the best from a SDSoC solution, we will also want to include DDR memory as this example will do.

If you do not yet have a suitable MicroBlaze design, the video below will walk you though how to create one quickly and easily.

Once we have our Vivado design completed, we need to set the IP Cache to being local to ensure there are no IP related issues with the SDSoC platform.

We do this through the settings IP tab:

With the IP location set correctly, the final stage before SDSoC platform generation is to verify the block diagram and generate the output products.

Once the design is verified and generated, we can start to create a SDSoC platform. We do this using the Vivado TCL Console.

To be able to add in accelerated functions, SDSoC needs to know about the AXI Interconnects, clocks, and resets available for its use.

The Vivado generated element of the SDSoC platform, therefore defines these available resources. The key minimum resources required for a platform are:

• Clock — Exported clock(s) for the SDSoC Platform, this must include the associated reset.

• AXI GPIO Master — This is used to control the datamover and accelerated IP.

• AXI HP Slave / MIG — This is used to transfer the data between DDR and accelerated IP.

A MicroBlaze solution is a little different from previous platforms we have generated for the Zynq and Zynq MPSoC.

This difference comes from the AXI ports available directly on the processor itself. The MicroBlaze processor only has one AXI Master port (M_AX_DP) for peripheral connections. As such, we need to share AXI interconnects to provide both the AXI Master and AXI Slave interfaces required by SDSoC.

Sharing AXI interconnects is very simple and means that, when we declare ports to the SDSoC platform, instead of declaring those on the MicroBlaze we declare the ports on the AXI Interconnect or Smart Interconnect.

Using the Vivado TCL Console and entering the commands below will create a simple MicroBlaze Device Support Archive file (DSA).

This DSA file shares the AXI Interconnects for the M_AXI_GP and S_AXI_HP / MIG along with declaring the clock and reset, plus many more hardware related configurations.

set_property PFM_NAME gensys2 [get_files design_1.bd] set_property PFM.CLOCK {ui_clk {id “1” is_default “true” proc_sys_reset “rst_mig_7series_0_100M”}} [get_bd_cells /mig_7series_0] set_property PFM.AXI_PORT {M05_AXI {memport “M_AXI_GP” }} [get_bd_cells /microblaze_0_axi_periph] set_property PFM.AXI_PORT {S03_AXI {memport “MIG” sptag “bank0” memory “mig_7series_0 memaddr”} }} [get_bd_cells /microblaze_0_axi_periph1] write_dsa -force gensys2.dsa validate_dsa gensys2.dsa -verbose

Once this is completed, Vivado will have generated the DSA file which we use to create the SDSoC platform.

Within SDSoC itself, the first thing we need to do is create a new platform. We do this by selecting:

File->New->SDx Project

This will open a dialog window. From there, select Platform Project and point to the DSA file just created on the second tab.

Once the DSA has been loaded and processed, SDSoC will open a new project under the project explorer.

Under this project structure, you will see a file with a file extension SPR.

This file defines how we create the platform. Double click to open it and you will see on the bottom the four steps to creating the platform.

As you go through each step, you will need to point to elements such as a linker file etc. These should exist from your initial testing of the MicroBlaze using SDK to check its basic functionality.

Once the final step has been completed in the SPR file, you should see a pop-up window saying the new custom platform is available for use.

We can confirm this by creating a new Application Project that uses it.

With the new project created, we are now in a position to write the software application and accelerate the functions if the performance requires it.

However before we accelerate any functions, as a first step with a new platform, I would recommend trying the project without any acceleration. This demonstrates the flow is OK and is faster to debug the application if there are any issues.

Once we are happy with the overall SW functionality, the next stage is to identify areas for acceleration using SDSoC’s ability to profile and trace the application.

When I did this with a very simple example, SDSoC created the Vivado platform below, which clearly shows the inclusion of the accelerator within the MicroBlaze System.

The ability to use SDSoC with our MicroBlaze solutions really enables us to optimize the performance of the overall solution, while also hopefully reducing the development time.

You can find out more about creating SDSoC Platforms here.

See My FPGA / SoC Projects: Adam Taylor on Hackster.io

Get the Code: ATaylorCEngFIET (Adam Taylor)

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