Small Stack Computing in VHDL

For a those of us that have been around a while, the Forth language has a special place in our hearts. For most, the Forth language shell interface to Open Firmware was something we delved into reluctantly—or sometimes with a certain amount of gleeful abandon—in an attempt to make our Sun Sparc Stations, or PowerPC-based Macintoshes, do things they weren’t quite intended to do. Or more usually, save them from a disaster.

However because there was never a standard reference implementation for Forth, and because the Forth virtual machine was relatively simple to implement, there are numerous implementations of the language. Amongst them is the J1 put together by James Bowman, a small Forth-based CPU implemented for FPGA. Implemented in just 200 lines of Verilog, a 50 MHz J1 CPU was used as a co-processor for the Gameduino.

The Gameduino. (📷: excamera)

But I haven’t come across another implementation in a while, so I was interested to be pointed at a Forth SoC written by Richard Howe in VHDL based on the J1 CPU called the H2.

Originally targeting the Nexys3 board — although future versions will target the Nexys 4, and the myStorm BlackIce boards — the project goal was to create a working version of the J1 along with a toolchain and a working version of Forth.

The H2 CPU inside a simulator. (📷: Richard Howe)

While the H2 CPU behaves very similarly to the J1 CPU there are some enhancements, and with the increasing number of FPGA boards starting to target makers, I think it’s going to be somewhat interesting to see if theoretically ‘obsolete’ languages—and associated virtual machines—like Forth will start being used more widely for homebrew CPUs.

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